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RightMark Memory Analyzer

Before this test packet was created there was no proper software for measuring vital system parameters such as CPU/Chipset/RAM providing steady and reliable (reproducible) test results and allowing for changing test parameters in a wide range. Vital low-level system characteristics include latency and real RAM bandwidth, average/minimal latency of different cache levels and its associativity, real L1-L2 cache bandwidth and TLB levels specs. Besides, these aspects are usually not paid sufficient attention in product technical documentation (CPU or chipset). Such test suite, which combines a good deal of subsets aimed at measuring objective system characteristics, is a must have for estimating crucial objective platform parameters.

RMMA provides you with the following platform information:

  • CPUID info, including CPU vendor, model and core name, family, model and stepping numbers, supported instruction set extensions, cache and TLB features;
  • Chipset (Northbridge and Southbridge) vendor and model name, AGP features, installed RAM type/size, current RAM timings;
  • Memory SPD (Serial Presence Detect) info, including module type/size, manufacturer, part number, attributes and timings;

Current release features memory timings reading/changing and memory SPD data reading on the following chipsets:

  • Intel 440, 810, 815, 830, 845, 848, 852, 855, 865, 875, 915, 925, 945 and 955 series; E7500, E7501, E7205, E7505, E7520 and E7525
  • AMD 751, 761, 762 and 8000
  • VIA VT82C597, VT82C691, VT8363, VT8601; K8T800 and K8T890 series
  • NVIDIA nForce2, nForce3, nForce4 series incl. nForce4 Intel Edition
  • ATI Radeon XPRESS200 AMD Edition

Limited experimental support is also available for:

  • VIA KT266, KM266, KN266, CLE266, KT400, PT800 and PT880 series
  • ATI Radeon XPRESS200 Intel Edition

Built-in RMMA microacrhitecture tests let you determine the most important low-level platform characteristics, which include:

  • Average and peak real RAM bandwidth;
  • L1/L2/L3 data cache size and hierarchy (inclusive/exclusive);
  • Average and minimal/maximal L1/L2/L3 data cache/RAM latency;
  • L1/L2/L3 data cache associativity;
  • L1-L2 and L2-L3 data cache bus bandwidth, data arrival delays;
  • I-ROB (instructions reorder buffer) depth;
  • L1 instructions cache size (including the "effective" size) and associativity;
  • Decode efficiency of various simple x86 (ALU/FPU/MMX) instructions;
  • D-TLB size and associativity (of each level);
  • I-TLB size and associativity (of each level).

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